1. Field of the Invention
The present invention relates to the technical field of dual-port static random access memory (SRAM) and, more particularly, to a multi-port (MP) SRAM with shared write bit-line architecture and selective read path for low power operation.
2. Description of Related Art
In recent years, the IC design demands more transmission bandwidths, such that the memory requirement is evolved from a single-port SRAM into a dual-port SRAM. Because the single-port SRAM does not have advanced feature of parallel operation for high speed communication and video applications, the dual-port SRAM that can perform a parallel read or write operation on different ports is proposed, but it introduces read/write disturb issues in the same row access.
Conventional multi-port SRAM design suffers write-disturb issues, when executing write operations with different ports at the same row. FIG. 1 schematically illustrates access of two adjacent bit cells of a conventional multi-port SRAM. When an A-port for writing and column 1 are selected, the bit cell with the same row in column 0 becomes write-half-select. Meanwhile, writing “0” in column 0 from B-port is difficult because the storage node is pre-charged to high through the activated write A-port word-line (WAWL). In this case, the bit cell in column 0 encounters a write-disturb issue. Conversely, when B-port for writing is activated and column 0 is selected, the bit cell in column 1 at the same row becomes write-half-select. Meanwhile, writing “0” in column 1 from A-port is difficult because the storage node is pre-charged to high through the activated write B-port word-line (WBWL). In this condition, the bit cell in column 1 encounters the write-disturb issue. As shown in FIG. 1, the two adjacent bit-cells encounter write-disturb issue.
In addition to the write-disturb issue, the write-half-select cell encounters a read static noise margin (RSNM) that is worse than the hold static noise margin (HSNM) issue. As shown in FIG. 1, when the bit cell in column 0 encounters a write-half-select issue, its storage node suffers disturbance noise from the bit-line pair, i.e. WABL0 and WABLB0, being pre-charged to high, despite the B port for writing being deactivated in column 0. The RSNM degrades most when both write ports activate at the same row.
When a write-half-select (dummy read) occurs in the cell of an unselected column, the RSNM becomes worse than the HSNM with the write bit-line of both write-ports deactivated, as the butterfly curve shown in FIG. 2, which schematically shows hold SNM and dummy-read SNM of conventional multi-port cell. As shown in FIG. 2, when the write bit-line of the A-port for writing is activated, the WABL and WABLB are pre-charged to high, disturbing the internal storage node. This in turn causes the RSNM to deteriorate, as shown by the triangle-dot butterfly curve shown in FIG. 2. When both ports are activated, deterioration of the RSNM is the worst, as shown by the circle-dot butterfly curve in FIG. 2.
Accordingly, it is desirable to provide a multi-port SRAM with shared write bit-line architecture and selective read path for low power operation to mitigate and/or obviate the aforementioned problems.